With semiconductor scaling, parasitic external resistance can pose significant challenges to achieving device performance. To increase performance, a channel strain can be placed on the device; however, it has been found that significant strain, e.g., approximately 50% of cSiGe strain, can be lost through cavity etching processes needed for source and drain formation. Some of the strain loss can be recovered, but such recovery is not a simple process.
For example, strain loss can be partially recovered by using embedded source and drain epitaxial processes. Alternatively, strain loss can be prevented using cladding techniques. However, cladding might not provide enough dopant source for lowering Ron. More specifically, with cladding processes, there is not enough SiGe:B volume to provide a junction overlap.